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authorFelix Held <felix-coreboot@felixheld.de>2021-11-25 15:41:02 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-11-30 14:39:54 +0000
commitefe402a3484bcd29cf8d36b770eda4c792fae05c (patch)
treea666ae626e8d8fbb922631f570173b27697c66fb /src/mainboard/google/brya/variants/redrix4es
parent783a8745451bac529c04e4855943bd0faa6be693 (diff)
soc/amd/common/block/include/lpc: add missing LPC_PCI_CONTROL bit defs
Both SPI_ROM_BIOS_SEMAPHORE and SPI_ROM_EC_SEMAPHORE bits in the LPC_PCI_CONTROL are defined in the Stoneyridge BKDG #55072 Rev 3.04, Raven1 and Picasso PPR #55570 Rev 3.18, Raven2 PPR #55772 Rev 3.08 and Cezanne PPR #56569 Rev 3.03 which are all platforms that use this code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I855e640d020daf21c9f5b2f62a2ad0fd0274a575 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/redrix4es')
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