diff options
| author | Wisley Chen <wisley.chen@quanta.corp-partner.google.com> | 2022-02-17 15:53:06 +0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 20:18:58 +0000 |
| commit | 03c0853f4d58c73a632f81cac2eb16b759d7f338 (patch) | |
| tree | 4650fd2a3c4a0acd2e98fac77efca722be07f533 /src/mainboard/google/brya/variants/redrix4es | |
| parent | 130de14a0590cf4dac8021bbf66850a26896d932 (diff) | |
mb/google/brya/redrix{4es}: Disable unused USB2/TCSS ports
Disable unused USB2/TCSS Ports.
BUG=b:217238553
TEST=FW_NAME=redrix emerge-brya coreboot
Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/redrix4es')
| -rw-r--r-- | src/mainboard/google/brya/variants/redrix4es/overridetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 22a9883374..5cb105df65 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -41,6 +41,11 @@ chip soc/intel/alderlake register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |