diff options
| author | Leo Chou <leo.chou@lcfc.corp-partner.google.com> | 2022-12-20 15:28:31 +0800 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-12-22 00:48:20 +0000 |
| commit | a86af49b9de653f5e32f160bd2abdb3e745235dd (patch) | |
| tree | 7833e6c812f27e6bb3b952dfb06d74563e98a114 /src/mainboard/google/brya/variants/pujjo/overridetree.cb | |
| parent | 0d76a30767a58a74f9cff8860dc7c19c848ee2bf (diff) | |
mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error
Configure eMMC DLL tuning values for Pujjo board Kioxia sku.
BUG=b:261676386
TEST=Use the value to boot on Pujjo successfully.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I46991f26571771620dcd94b90e1112484ade63bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/pujjo/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjo/overridetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 3997a815c8..1bba29c1bc 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -75,7 +75,7 @@ chip soc/intel/alderlake # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D1B" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B" # EMMC RX CMD/DATA Delay 2 # Refer to EDS-Vol2-42.3.12. @@ -86,7 +86,7 @@ chip soc/intel/alderlake # 11: Reserved # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. - register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10049" + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023" # EMMC Rx Strobe Delay # Refer to EDS-Vol2-42.3.11. |