diff options
| author | Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> | 2021-12-14 17:00:56 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-20 17:45:48 +0000 |
| commit | 814069174279b02f63660cbff6a002904049828a (patch) | |
| tree | 24e3b8eaf0cba04ab1d2e84d7e45d8c4bde027cd /src/mainboard/google/brya/variants/primus4es | |
| parent | fba3668f5a8dedb64363dcf469bac677e4571005 (diff) | |
mb/google/brya/var/primus: Update thermal table for primus
- Because primus have five sensors,we need to define 5 sensors.
BUG=b:200836803
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/primus4es')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus4es/overridetree.cb | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index 22d61b0a2e..ce6bec542f 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -84,19 +84,22 @@ chip soc/intel/alderlake device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""SSD"" - register "options.tsr[1].desc" = ""CHARGER"" - register "options.tsr[2].desc" = ""MEMORY"" - register "options.tsr[3].desc" = ""TYPEC"" + register "options.tsr[0].desc" = ""CPU"" + register "options.tsr[1].desc" = ""SSD"" + register "options.tsr[2].desc" = ""CHARGER"" + register "options.tsr[3].desc" = ""MEMORY"" + register "options.tsr[4].desc" = ""TYPEC"" # TODO: below values are initial reference values only ## Passive Policy register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 90, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000), + [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000), + }" ## Critical Policy @@ -106,6 +109,7 @@ chip soc/intel/alderlake [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN), [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN), + [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN), }" register "controls.power_limits" = "{ |