diff options
| author | Casper Chang <casper_chang@wistron.corp-partner.google.com> | 2021-11-10 09:52:18 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2021-11-12 14:55:15 +0000 |
| commit | b139e6b2a38373a5769d1273dc04ac0f7b617a53 (patch) | |
| tree | f0569d660779db479437ce34f3f5cfd39491eaac /src/mainboard/google/brya/variants/primus/overridetree.cb | |
| parent | 09a66ace7eef4a88d168b7edfb1cb0546e48c34d (diff) | |
mb/google/brya/var/primus: Disable autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/primus/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/overridetree.cb | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index c4debb49da..81dc1c03aa 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -22,7 +22,16 @@ fw_config end chip soc/intel/alderlake - + # This disabled autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" register "SaGv" = "SaGv_Enabled" register "MaxDramSpeed" = "3733" |