mb/google/nissa: Simplify LTE GPIO config using pad-based overrides

Currently, to enable/disable LTE based on fw_config on nissa, we have
two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to
prevent the SAR interrupt pin GPP_H19 from floating for the short period
of time between enabling it in gpio.c and disabling it in fw_config.c
(see CB:64270 for more details).

With the new pad-based GPIO overrides (CB:64712), this is no longer an
issue since the gpio.c and fw_config.c overrides are applied at the same
time. So simplify the LTE GPIO configuration by enabling all the LTE
pins in the variant gpio.c, then disabling them in fw_config.c if
needed.

BUG=b:231690996
TEST=LTE still works on nivviks

Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 32 insertions, 15 deletions

diff --git a/src/mainboard/google/brya/variants/nivviks/fw_config.c b/src/mainboard/google/brya/variants/nivviks/fw_config.c
index 3362f3d825..654d2f41fa 100644
--- a/src/mainboard/google/brya/variants/nivviks/fw_config.c
+++ b/src/mainboard/google/brya/variants/nivviks/fw_config.c
@@ -3,31 +3,33 @@
 #include <baseboard/gpio.h>
 #include <baseboard/variants.h>
 #include <boardid.h>
-#include <bootstate.h>
 #include <console/console.h>
 #include <fw_config.h>
 
-static const struct pad_config lte_enable_pads[] = {
-	/* A8  : WWAN_RF_DISABLE_ODL */
-	PAD_CFG_GPO(GPP_A8, 1, DEEP),
-	/* H19 : SOC_I2C_SUB_INT_ODL */
-	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
-	/* H23 : WWAN_SAR_DETECT_ODL */
-	PAD_CFG_GPO(GPP_H23, 1, DEEP),
-};
-
 static const struct pad_config lte_disable_pads_nivviks[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
 	/* D6  : WWAN_EN */
 	PAD_NC(GPP_D6, NONE),
 	/* F12 : WWAN_RST_L */
 	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
 };
 
 static const struct pad_config lte_disable_pads_nirwen[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_NC(GPP_A8, NONE),
 	/* E13  : WWAN_EN */
 	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* F12 : WWAN_RST_L */
 	PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_NC(GPP_H19, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_NC(GPP_H23, NONE),
 };
 
 static const struct pad_config sd_disable_pads[] = {
@@ -94,11 +96,7 @@ static const struct pad_config nvme_disable_pads[] = {
 
 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
 {
-	if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
-		printk(BIOS_INFO, "Enable LTE-related GPIO pins.\n");
-		gpio_padbased_override(padbased_table, lte_enable_pads,
-						ARRAY_SIZE(lte_enable_pads));
-	} else {
+	if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
 		if (board_id() >= 2) {
 			printk(BIOS_INFO, "Disable LTE-related GPIO pins on nirwen.\n");
 			gpio_padbased_override(padbased_table, lte_disable_pads_nirwen,
diff --git a/src/mainboard/google/brya/variants/nivviks/gpio.c b/src/mainboard/google/brya/variants/nivviks/gpio.c
index 0b19a14d0b..27409b64a1 100644
--- a/src/mainboard/google/brya/variants/nivviks/gpio.c
+++ b/src/mainboard/google/brya/variants/nivviks/gpio.c
@@ -8,6 +8,8 @@
 
 /* Pad configuration in ramstage for nivviks board_id = 0 */
 static const struct pad_config board_id0_overrides[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
 	/* D6  : WWAN_EN */
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
 	/* D7  : WLAN_CLKREQ_ODL */
@@ -16,6 +18,10 @@ static const struct pad_config board_id0_overrides[] = {
 	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
 	/* H3  : WLAN_PCIE_WAKE_ODL */
 	PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
 	/* R4 : I2S2_SCLK ==> I2S_SPK_BCLK_R */
 	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2),
 	/* R5 : I2S2_SFRM ==> I2S_SPK_LRCK_R */
@@ -40,6 +46,8 @@ static const struct pad_config board_id0_overrides[] = {
 
 /* Pad configuration in ramstage for nivviks board_id >= 1 */
 static const struct pad_config override_gpio_table[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
 	/* D6  : WWAN_EN */
 	PAD_CFG_GPO(GPP_D6, 1, DEEP),
 	/* D7  : WLAN_CLKREQ_ODL */
@@ -48,6 +56,10 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
 	/* H3  : WLAN_PCIE_WAKE_ODL */
 	PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
 
 	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 	/* BT_I2S_BCLK */
@@ -70,6 +82,8 @@ static const struct pad_config override_gpio_table[] = {
 
 /* Pad configuration in ramstage for nirwen */
 static const struct pad_config override_gpio_table_nirwen[] = {
+	/* A8  : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_A8, 1, DEEP),
 	/* B4  : SSD_PERST_L */
 	PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
 	/* D6  : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
@@ -86,6 +100,11 @@ static const struct pad_config override_gpio_table_nirwen[] = {
 	PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
 	/* H3  : WLAN_PCIE_WAKE_ODL */
 	PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG),
+	/* H19 : SOC_I2C_SUB_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
+	/* H23 : WWAN_SAR_DETECT_ODL */
+	PAD_CFG_GPO(GPP_H23, 1, DEEP),
+
 	/* Configure the virtual CNVi Bluetooth I2S GPIO pads */
 	/* BT_I2S_BCLK */
 	PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),