diff options
| author | Kevin Chiu <kevin.chiu.17802@gmail.com> | 2022-10-28 13:05:44 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-08 00:27:58 +0000 |
| commit | 9429844f816c7ed544e8ffeb6f23294213eb85c2 (patch) | |
| tree | e2e38797fe200cf4812dc74a1dc5be0fe6b90f05 /src/mainboard/google/brya/variants/lisbon | |
| parent | 4d23b9f18b020aa266ee9b4eac5898803cd4f2fd (diff) | |
mb/google/brya/var/lisbon: Disable thunderbolt ports
Lisbon doesn't support thunderbolt.
BUG=b:246657849
TEST=FW_NAME=lisbon emerge-brask coreboot
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: Iac44315d000c3c0c572efb00e877d039e0308455
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68916
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/lisbon')
| -rw-r--r-- | src/mainboard/google/brya/variants/lisbon/overridetree.cb | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/src/mainboard/google/brya/variants/lisbon/overridetree.cb b/src/mainboard/google/brya/variants/lisbon/overridetree.cb index 23c346175c..fc285639cf 100644 --- a/src/mainboard/google/brya/variants/lisbon/overridetree.cb +++ b/src/mainboard/google/brya/variants/lisbon/overridetree.cb @@ -150,13 +150,12 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref tcss_dma0 on - chip drivers/intel/usb4/retimer - register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" - use tcss_usb3_port1 as dfp[0].typec_port - device generic 0 on end - end - end + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" |