diff options
| author | Robert Chen <robert.chen@quanta.corp-partner.google.com> | 2023-02-09 20:55:21 -0500 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-13 14:43:44 +0000 |
| commit | 0e0f9e51c4c4f190cbe7ef5bffa138601c644d3c (patch) | |
| tree | bcf6a7edbc52dd179216e241ec134ccf0ab5f81c /src/mainboard/google/brya/variants/lisbon | |
| parent | 3eb17b91daac0b3acaffb01568d724d23c6f0eea (diff) | |
mb/google/brya/var/lisbon: Update gpio table
eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH.
BUG=b:263548436
TEST=emerge-brask coreboot
Change-Id: Iffbc9dc932325cdd2176b36795a2ff1b3690fbf8
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72941
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/lisbon')
| -rw-r--r-- | src/mainboard/google/brya/variants/lisbon/gpio.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/lisbon/gpio.c b/src/mainboard/google/brya/variants/lisbon/gpio.c index 1dfef5ceb0..443d59c607 100644 --- a/src/mainboard/google/brya/variants/lisbon/gpio.c +++ b/src/mainboard/google/brya/variants/lisbon/gpio.c @@ -25,7 +25,7 @@ static const struct pad_config override_gpio_table[] = { /* B2 : VRALERT# ==> M2_SSD_PLA_L */ PAD_NC(GPP_B2, NONE), /* B3 : PROC_GP2 ==> EMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B3, 1, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */ PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */ @@ -91,8 +91,6 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* A21 : DDPC_CTRCLK ==> EN_PP3300_EMMC */ PAD_CFG_GPO(GPP_A21, 1, DEEP), - /* B3 : PROC_GP2 ==> EMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 0, DEEP), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ @@ -136,8 +134,6 @@ static const struct pad_config early_gpio_table[] = { }; static const struct pad_config romstage_gpio_table[] = { - /* B3 : PROC_GP2 ==> EMMC_PERST_L */ - PAD_CFG_GPO(GPP_B3, 1, DEEP), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 1, DEEP), }; |