diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2021-11-10 14:26:27 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-11-15 09:46:30 +0000 |
| commit | 53075c720b3031798980797ec5d14bac93f9424e (patch) | |
| tree | 6dedea93bbba9bc3c389a5cba67de126e76a5f84 /src/mainboard/google/brya/variants/kano | |
| parent | b8f0539d2d27a61f979b766e3431655288f974df (diff) | |
mb/google/brya/var/kano: Add thermal sensor settings
Kano has 3 thermal sensors, so add the missing sensor settings.
BUG=b:205648035
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/kano')
| -rw-r--r-- | src/mainboard/google/brya/variants/kano/overridetree.cb | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/mainboard/google/brya/variants/kano/overridetree.cb b/src/mainboard/google/brya/variants/kano/overridetree.cb index 8aca8b4584..499dad2c41 100644 --- a/src/mainboard/google/brya/variants/kano/overridetree.cb +++ b/src/mainboard/google/brya/variants/kano/overridetree.cb @@ -49,7 +49,8 @@ chip soc/intel/alderlake chip drivers/intel/dptf ## sensor information register "options.tsr[0].desc" = ""DRAM"" - register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" # TODO: below values are initial reference values only ## Active Policy @@ -68,7 +69,8 @@ chip soc/intel/alderlake register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), - [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000), }" ## Critical Policy @@ -76,6 +78,7 @@ chip soc/intel/alderlake [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN), }" register "controls.power_limits" = "{ |