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authorYunlong Jia <yunlong.jia@ecs.corp-partner.google.com>2023-07-24 03:06:50 +0000
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-07-28 14:22:55 +0000
commitaae52ef4b35a9dd2b27c2fe28083dee4e87e8d05 (patch)
tree25834c96a1ca59240fdfb12de3ad840b15817037 /src/mainboard/google/brya/variants/gothrax/gpio.c
parentf4e3f15b44f0d0e117781d194f700cc19b3a88c7 (diff)
mb/google/nissa/var/gothrax: Tune SX9324 P-sensor configuration
Update SX9324 register settings based on tuning value from SEMTECH. - Enable GPP_B5/GPP_B6 - Enable GPP_H19 open irq - Adjust register reg_afe_ctrl0/reg_afe_ctrl3/reg_afe_ctrl4 BUG=b:292016304 BRANCH=None TEST=Check register settings and confirm P-sensor function can work. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I6f15f7a7c428aee45d35830574ef84aefcae6401 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76711 Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/gothrax/gpio.c')
-rw-r--r--src/mainboard/google/brya/variants/gothrax/gpio.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/gothrax/gpio.c b/src/mainboard/google/brya/variants/gothrax/gpio.c
index ab3b641f8c..0bf1b52ddb 100644
--- a/src/mainboard/google/brya/variants/gothrax/gpio.c
+++ b/src/mainboard/google/brya/variants/gothrax/gpio.c
@@ -21,11 +21,6 @@ static const struct pad_config override_gpio_table[] = {
/* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */
PAD_CFG_GPO(GPP_A22, 1, DEEP),
- /* B5 : SOC_I2C_SUB_SDA */
- PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
- /* B6 : SOC_I2C_SUB_SCL */
- PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
-
/* C1 : SMBDATA ==> TCHSCR_RST_L */
PAD_CFG_GPO(GPP_C1, 1, DEEP),
@@ -36,6 +31,8 @@ static const struct pad_config override_gpio_table[] = {
/* D16 : EN_PP1800_PP1200_WCAM_X */
PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
+ /* H19 : SOC_I2C_SUB_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE),
/* H22 : WCAM_MCLK_R */
PAD_NC(GPP_H22, NONE),
};