diff options
| author | Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> | 2021-11-23 22:54:01 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-02 20:51:48 +0000 |
| commit | 44577683008010b4470c42bf7c10ba9d92780f30 (patch) | |
| tree | 0189a723d7b3a51b658533d475ba350113030858 /src/mainboard/google/brya/variants/gimble/overridetree.cb | |
| parent | cca657f8984ac7e2b0ac499fc3efafe806d9198c (diff) | |
mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C
DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap
TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C,
need change I2C map, sch amd GPIO map. b/196293623
BUG=b:207613972
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/gimble/overridetree.cb')
| -rw-r--r-- | src/mainboard/google/brya/variants/gimble/overridetree.cb | 44 |
1 files changed, 37 insertions, 7 deletions
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 8b6daf2b29..47e81d8687 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -40,6 +40,36 @@ chip soc/intel/alderlake register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio and WFC | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | SAR0 | + #| I2C3 | Touchscreen | + #| | | + #| | | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf @@ -156,6 +186,13 @@ chip soc/intel/alderlake end end #I2C0 device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on chip drivers/i2c/hid register "generic.hid" = ""ELAN9050"" register "generic.desc" = ""ELAN Touchscreen"" @@ -176,13 +213,6 @@ chip soc/intel/alderlake device i2c 0x15 on end end end - device ref i2c3 on - chip drivers/i2c/tpm - register "hid" = ""GOOG0005"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" - device i2c 50 on end - end - end device ref i2c5 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" |