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authorJack Rosenthal <jrosenth@chromium.org>2022-07-18 13:54:09 -0600
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-07-22 03:25:10 +0000
commit15e4c0a23f93835a7f4e3756705eaa11a3a5bc2f (patch)
tree7bca78214b96e6ec15379514af19c50ae1f6afb7 /src/mainboard/google/brya/variants/ghost/overridetree.cb
parenta8a673863186dd5468c7835270322bf202d3d9f2 (diff)
mb/google/brya/var/ghost: Split ghost4adl into 3 variants
We plan to make 3 firmwares which differ only by Kconfig options and can share a common variant directory. ghost4adl: Board with an ADL chip. ghost4es: Board near identical but has RPL-ES chip. ghost: Will have final RPL silicon. Since they will only differ by Kconfig options and Intel binary blobs, let's not duplicate the variant directory but instead share it in common. BUG=b:239456576 BRANCH=firmware-brya-14505.B TEST="make menuconfig", verify layout of board selection Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I94f2048bbe6675a807f8eba986a1ded0a4167733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/ghost/overridetree.cb')
-rw-r--r--src/mainboard/google/brya/variants/ghost/overridetree.cb192
1 files changed, 192 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/ghost/overridetree.cb b/src/mainboard/google/brya/variants/ghost/overridetree.cb
new file mode 100644
index 0000000000..b20593a479
--- /dev/null
+++ b/src/mainboard/google/brya/variants/ghost/overridetree.cb
@@ -0,0 +1,192 @@
+chip soc/intel/alderlake
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| GSPI1 | FPMCU |
+ #| I2C0 | Audio |
+ #| I2C1 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| I2C2 | Misc (Cam, Display, LED) |
+ #| I2C3 | Touchscreen |
+ #| I2C4 | NC |
+ #| I2C5 | Touchpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .i2c[0] = {
+ .speed = I2C_SPEED_STANDARD,
+ .speed_config[0] = {
+ .speed = I2C_SPEED_STANDARD,
+ .scl_lcnt = 45,
+ .scl_hcnt = 33,
+ .sda_hold = 20,
+ },
+ },
+ .i2c[1] = {
+ .early_init = 1,
+ .speed = I2C_SPEED_STANDARD,
+ .rise_time_ns = 600,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_STANDARD,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_STANDARD,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_STANDARD,
+ .rise_time_ns = 650,
+ .fall_time_ns = 400,
+ .data_hold_time_ns = 50,
+ },
+ }"
+
+ # I2C Port Config
+ register "serial_io_i2c_mode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexI2C7] = PchSerialIoDisabled,
+ }"
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # USB2_C1
+ register "usb2_ports[2]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[3]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # DCI port
+ register "usb2_ports[5]" = "USB2_PORT_EMPTY"
+ register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+
+ register "usb3_ports[0]" = "USB3_PORT_EMPTY"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # DCI port
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY"
+
+ register "tcss_ports[0]" = "TCSS_PORT_EMPTY"
+ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # TypeC C1
+ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" # TypeC C0
+
+ device domain 0 on
+ device ref cnvi_wifi on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end
+ device ref pcie_rp6 off end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port2 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref tcss_dma1 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
+ use tcss_usb3_port3 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref i2c1 on
+ chip drivers/i2c/tpm
+ register "hid" = ""GOOG0005""
+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
+ device i2c 50 on end
+ end
+ end
+ device ref gspi1 on
+ chip drivers/spi/acpi
+ register "name" = ""CRFP""
+ register "hid" = "ACPI_DT_NAMESPACE_HID"
+ register "uid" = "1"
+ register "compat_string" = ""google,cros-ec-spi""
+ register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
+ register "wake" = "GPE0_DW2_15"
+ device spi 0 on end
+ end # FPMCU
+ end
+ device ref pch_espi on
+ chip ec/google/chromeec
+ # Replicate Brya, except we have 2 ports instead of 3.
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ device pnp 0c09.0 on end
+ end
+ end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ # C0: Left side (on DB)
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port3 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ # C1: Right side (on MLB)
+ use usb2_port2 as usb2_port
+ use tcss_usb3_port2 as usb3_port
+ device generic 1 alias conn1 on end
+ end
+ end
+ end
+ end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0 (DB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ # USB C0 is on the LEFT panel, LEFT side (i.e. rear)
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref tcss_usb3_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C1 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear)
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
+ end
+ end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0 (DB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ # USB C0 is on the LEFT panel, LEFT side (i.e. rear)
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C1 (MLB)""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ # USB C1 is on the RIGHT panel, RIGHT side (i.e. rear)
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port2 on end
+ end
+ end
+ end
+ end
+ end
+end