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authorEric Lai <ericr_lai@compal.corp-partner.google.com>2022-01-07 12:13:01 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-01-14 14:28:43 +0000
commita92589bc5c403f1633dc87a5fa9d38836db131dc (patch)
treefe614e16250ea536a061aacc2bfb6dcbeedc257f /src/mainboard/google/brya/variants/felwinter
parentdb29b3765b1d760c4fff4e21b27a4aabe218f4ab (diff)
mb/google/brya: move SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES to common
ADL support USB4/TBT. Select it will reserve PCI buses and hotplug mem and prefetch mem. BUG=b:206739931 TEST=build PASS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1171981c1318c2ecb65ba7959c4de9b5e179514e Reviewed-on: https://review.coreboot.org/c/coreboot/+/60885 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/felwinter')
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