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authorMatt DeVillier <matt.devillier@gmail.com>2023-01-17 13:44:23 -0600
committerMatt DeVillier <matt.devillier@amd.corp-partner.google.com>2023-05-04 21:02:44 +0000
commit3f3dc504e9d2ce084e00cc0911bebf042056a78c (patch)
tree7f450dcbd896b065e7dd416015e6008cc3ed9c72 /src/mainboard/google/brya/variants/felwinter/overridetree.cb
parent35470e1604ef2d65c69b05a39b4f4dbe3dc86c01 (diff)
mb/google/brya: Add SOF chip driver
Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on banshee and osiris variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Diffstat (limited to 'src/mainboard/google/brya/variants/felwinter/overridetree.cb')
-rw-r--r--src/mainboard/google/brya/variants/felwinter/overridetree.cb6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/felwinter/overridetree.cb b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
index e5a64b1021..9e7e739f84 100644
--- a/src/mainboard/google/brya/variants/felwinter/overridetree.cb
+++ b/src/mainboard/google/brya/variants/felwinter/overridetree.cb
@@ -316,6 +316,12 @@ chip soc/intel/alderlake
register "sdmode_delay" = "5"
device generic 0 on end
end
+ chip drivers/sof
+ register "spkr_tplg" = "max98360a"
+ register "jack_tplg" = "rt5682"
+ register "mic_tplg" = "_2ch_pdm1"
+ device generic 0 on end
+ end
end
device ref pch_espi on
chip ec/google/chromeec