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authorWon Chung <wonchung@google.com>2022-05-27 22:15:43 +0000
committerMartin L Roth <gaumless@tutanota.com>2022-06-01 01:44:34 +0000
commit7303e3dec8390d7ba0da7ee4cd49612e9e384191 (patch)
tree8ade00bbcca11daa11d643d4793817f4ad9eee3d /src/mainboard/google/brya/variants/craask
parent5cfd750899eb7905dc0da3c8914b3cc1c77470cc (diff)
mb/google/brya/var/craask: Add ACPI _PLD custom values
This patch uses ACPI _PLD macros to add custom values for USB ports. +----------------+ | | | Screen | | | +----------------+ C0 | | C1 A0 | MLB DB | A1 | | +----------------+ BUG=b:232256907 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/craask')
-rw-r--r--src/mainboard/google/brya/variants/craask/overridetree.cb24
1 files changed, 16 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb
index 01f10e1bc7..ac9173226a 100644
--- a/src/mainboard/google/brya/variants/craask/overridetree.cb
+++ b/src/mainboard/google/brya/variants/craask/overridetree.cb
@@ -286,13 +286,15 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(1, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(2, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref tcss_usb3_port2 on end
end
end
@@ -304,25 +306,29 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C0 (MLB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(1, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))"
device ref usb2_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-C Port C1 (DB)""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
- register "group" = "ACPI_PLD_GROUP(2, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))"
device ref usb2_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_A"
- register "group" = "ACPI_PLD_GROUP(3, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb2_port3 on end
end
chip drivers/usb/acpi
register "desc" = ""USB2 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_A"
- register "group" = "ACPI_PLD_GROUP(4, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb2_port4 on
probe DB_USB DB_1C_1A
end
@@ -349,13 +355,15 @@ chip soc/intel/alderlake
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)""
register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(3, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))"
device ref usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A1 (DB)""
register "type" = "UPC_TYPE_USB3_A"
- register "group" = "ACPI_PLD_GROUP(4, 1)"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))"
device ref usb3_port2 on
probe DB_USB DB_1C_1A
end