diff options
| author | Tyler Wang <tyler.wang@quanta.corp-partner.google.com> | 2022-04-28 09:34:57 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-21 16:16:53 +0000 |
| commit | 10fb9c7f363b22a87117d8f404d9f64d7e3c28e4 (patch) | |
| tree | 7392f5b4dfa544980bb7e2ed239fdea6902908ef /src/mainboard/google/brya/variants/craask | |
| parent | 03bdf47102db65bce3bd7bc766da01ef2cf504b4 (diff) | |
mb/google/nissa/var/craask: Switch LTE-related GPIOs settings based on fw_config
If the LTE USB DB is connected, enable LTE-related settings.
Otherwise, disable LTE-related settings.
BUG=b:229938024, b:229048361, b:229040345
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I37719cee48370a04534067aa64a3aa77e453948a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/craask')
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/fw_config.c | 34 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/gpio.c | 14 |
3 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/craask/Makefile.inc b/src/mainboard/google/brya/variants/craask/Makefile.inc index ebd95c4048..8ae0e3b61c 100644 --- a/src/mainboard/google/brya/variants/craask/Makefile.inc +++ b/src/mainboard/google/brya/variants/craask/Makefile.inc @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c + romstage-y += gpio.c + +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c new file mode 100644 index 0000000000..ad279696c4 --- /dev/null +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> + +static const struct pad_config lte_enable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), +}; + +static const struct pad_config lte_disable_pads[] = { + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC(GPP_F12, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Enable LTE-related GPIO pins.\n"); + gpio_configure_pads(lte_enable_pads, ARRAY_SIZE(lte_enable_pads)); + } else { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index 93ae7760b5..2ca514f36b 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -5,6 +5,14 @@ #include <commonlib/helpers.h> #include <soc/gpio.h> +/* Pad configuration in ramstage for craask */ +static const struct pad_config override_gpio_table[] = { + /* D6 : WWAN_EN */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), +}; + /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* F12 : GSXDOUT ==> WWAN_RST_L */ @@ -36,6 +44,12 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_H12, 1, DEEP), }; +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + const struct pad_config *variant_early_gpio_table(size_t *num) { *num = ARRAY_SIZE(early_gpio_table); |