diff options
| author | Reka Norman <rekanorman@google.com> | 2022-08-16 10:48:51 +1000 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-17 23:27:19 +0000 |
| commit | 054620dcdc4d9bda47b245ad58d2c6c5f8f79e86 (patch) | |
| tree | 781c28c46050706f73822633493c91679cab7f1b /src/mainboard/google/brya/variants/craask | |
| parent | 9c63fd5ad28a6b32397d61bcfc5f5779c10c794a (diff) | |
mb/google/nissa: Simplify LTE GPIO config using pad-based overrides
Currently, to enable/disable LTE based on fw_config on nissa, we have
two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to
prevent the SAR interrupt pin GPP_H19 from floating for the short period
of time between enabling it in gpio.c and disabling it in fw_config.c
(see CB:64270 for more details).
With the new pad-based GPIO overrides (CB:64712), this is no longer an
issue since the gpio.c and fw_config.c overrides are applied at the same
time. So simplify the LTE GPIO configuration by enabling all the LTE
pins in the variant gpio.c, then disabling them in fw_config.c if
needed.
BUG=b:231690996
TEST=LTE still works on nivviks
Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/craask')
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/fw_config.c | 22 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/gpio.c | 6 |
2 files changed, 13 insertions, 15 deletions
diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index bae6d3c276..602eeabfe1 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -2,24 +2,20 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> -#include <bootstate.h> #include <console/console.h> #include <fw_config.h> -static const struct pad_config lte_enable_pads[] = { - /* A8 : WWAN_RF_DISABLE_ODL */ - PAD_CFG_GPO(GPP_A8, 1, DEEP), - /* H19 : SOC_I2C_SUB_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), - /* H23 : WWAN_SAR_DETECT_ODL */ - PAD_CFG_GPO(GPP_H23, 1, DEEP), -}; - static const struct pad_config lte_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), /* D6 : WWAN_EN */ PAD_NC(GPP_D6, NONE), /* F12 : WWAN_RST_L */ PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), }; static const struct pad_config wfc_disable_pads[] = { @@ -48,11 +44,7 @@ static const struct pad_config sd_disable_pads[] = { void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { - if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { - printk(BIOS_INFO, "Enable LTE-related GPIO pins.\n"); - gpio_padbased_override(padbased_table, lte_enable_pads, - ARRAY_SIZE(lte_enable_pads)); - } else { + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index cb5b996328..00d18852b8 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -7,6 +7,8 @@ /* Pad configuration in ramstage for craask */ static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), /* D6 : WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* D7 : WLAN_CLKREQ_ODL */ @@ -15,6 +17,10 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* H3 : WLAN_PCIE_WAKE_ODL */ PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), }; /* Early pad configuration in bootblock */ |