diff options
| author | Zhuohao Lee <zhuohao@chromium.org> | 2021-12-14 14:35:52 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-20 17:45:28 +0000 |
| commit | fba3668f5a8dedb64363dcf469bac677e4571005 (patch) | |
| tree | 983d60213e85c37ae2bd45094d4f6e31fc29b08c /src/mainboard/google/brya/variants/brask | |
| parent | aed38a94e3488a2ed4465b208eb5f9df8af10d5f (diff) | |
mb/google/brya/variants/brask: Disable autonomous GPIO power management
We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device
executed the reboot test even though we have updated the Cr50 firmware
to the latest version 0.6.70. Besides, we also experienced the device
failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the
factory. In order to fix these issues, we disable the gpio power
management from the devicetree.
BUG=b:210540890
TEST=reboot 100 cycles without the error message.
Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/brask')
| -rw-r--r-- | src/mainboard/google/brya/variants/brask/overridetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/brask/overridetree.cb b/src/mainboard/google/brya/variants/brask/overridetree.cb index 63a683dca4..a7b763f774 100644 --- a/src/mainboard/google/brya/variants/brask/overridetree.cb +++ b/src/mainboard/google/brya/variants/brask/overridetree.cb @@ -1,4 +1,14 @@ chip soc/intel/alderlake + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses; need to clarify + # the minimum PCH IRQ pulse width with Intel, b/180111628 + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" device domain 0 on device ref dtt on chip drivers/intel/dptf |