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authorKane Chen <kane.chen@intel.corp-partner.google.com>2021-11-29 18:31:02 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-12-03 15:38:00 +0000
commit2a30359d5a8717825f7e7fb43e1feffa951b275c (patch)
treea736f6943118abea9249ad3961ca74d4dcda66c5 /src/mainboard/google/brya/variants/brask/gpio.c
parentea1bb5f7de084ee812a3094fd1a4876c91ef70e6 (diff)
mb/google/brya/var/brask: Set vGPIO reset type
Due to the vGPIO is not reset when we power on through S5, we would met MCA when PCIE send L1 request without following Ack BUG=b:207625007 TEST=S0->S3->S5->power key->S3->S0, see if boot up normal Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79 Signed-off-by: Curtis Chen <curtis.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/brask/gpio.c')
-rw-r--r--src/mainboard/google/brya/variants/brask/gpio.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/src/mainboard/google/brya/variants/brask/gpio.c b/src/mainboard/google/brya/variants/brask/gpio.c
index b57c80e207..da17230869 100644
--- a/src/mainboard/google/brya/variants/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/brask/gpio.c
@@ -40,26 +40,26 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_H13, 1, DEEP),
/* CPU PCIe VGPIO for PEG60 */
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, DEEP, NF1),
- PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, DEEP, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
+ PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
};
static const struct pad_config romstage_gpio_table[] = {