diff options
| author | Nick Vaccaro <nvaccaro@google.com> | 2023-08-21 09:50:12 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2023-08-22 16:11:06 +0000 |
| commit | eb08ae4ce13b6e6290fdfb31fbb87db440940a84 (patch) | |
| tree | e19eeac2434d5cdfa310e873b7784b5cd25b1bb3 /src/mainboard/google/brya/variants/baseboard | |
| parent | fae1eb3e667c59df0f39725785190fca31e51fc1 (diff) | |
mb/google/brya/var/bb/brask: enable HDMI gpios early
Add some HDMI-related gpios that are needed for early sign-of-life
to the early_graphics_gpio_table array so that SOL will show up on
HDMI ports.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage` and verify it builds
without error.
Change-Id: Ic36a636e68c2d457f40329a2e9c69dab5bbba41f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77353
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/gpio.c | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c index e81bd05942..3d667b935e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c @@ -2,6 +2,7 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <intelblocks/early_graphics.h> #include <types.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -403,6 +404,33 @@ static const struct pad_config romstage_gpio_table[] = { PAD_CFG_GPO(GPP_B4, 1, DEEP), }; +const struct pad_config early_graphics_gpio_table[] = { + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* D1 : ISH_GP1 ==> HDMI_IN_PLUGIN */ + PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), + /* D11 : ISH_SPI_MISO ==> HDMIA_CTRLCLK */ + PAD_CFG_NF_LOCK(GPP_D11, NONE, NF2, LOCK_CONFIG), + /* D12 : ISH_SPI_MOSI ==> HDMIA_CTRLDATA */ + PAD_CFG_NF_LOCK(GPP_D12, NONE, NF2, LOCK_CONFIG), + /* E14 : DDSP_HPDA ==> HDMIA_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + /* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDIB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_graphics_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_graphics_gpio_table); + return early_graphics_gpio_table; +} + const struct pad_config *__weak variant_gpio_table(size_t *num) { *num = ARRAY_SIZE(gpio_table); |