diff options
| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2021-09-15 16:03:40 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-27 13:33:23 +0000 |
| commit | 658d7c56b8621b1682ce0f2e457e6abce7308851 (patch) | |
| tree | c01eaa76481d7cdcbe00a65c3e03f2576542b615 /src/mainboard/google/brya/variants/baseboard | |
| parent | b3ffff87dd1e01eb20240279f5d88707475c1428 (diff) | |
mb/google/brya: Correct SSD power sequence
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PREST should be sequenced after power enable.
BUG=b:199822704
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If0a9e36cda4dc91bbccec02f39ccb9b658d24056
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/gpio.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index c11cf42254..73fad72480 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -388,6 +388,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), /* B8 : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */ |