diff options
| author | Jakub Czapiga <jacz@semihalf.com> | 2023-01-04 17:31:03 +0000 |
|---|---|---|
| committer | Jakub Czapiga <jacz@semihalf.com> | 2023-01-04 20:30:38 +0000 |
| commit | 43b7e60e3eba7787c3adc892e1ca902e1a918c2a (patch) | |
| tree | 9f5e6a7076ee15536f77096b8de4301e31ff82b0 /src/mainboard/google/brya/variants/baseboard | |
| parent | e45f70423e5da8509bae83aba84b08f8fc0f624e (diff) | |
Revert "mb/google/brya: Add romstage early graphics for brya"
This reverts commit 96d9b756690839c17b307a93b8a1898bd1c02ff5.
Reason for revert: Merged out of order, broke tree
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Iac2d78f2d6c687f52dc720e8d8dcb5cf7a171c9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71280
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 32 |
1 files changed, 1 insertions, 31 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index efc2fcbc98..70e7779545 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -123,37 +123,7 @@ chip soc/intel/alderlake }" device domain 0 on - # The timing values can be derived from datasheet of display panel - # You can use EDID string to identify the type of display on the board - # use below command to get display info from EDID - # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid - - # refer to display PRM document (Volume 2b: Command Reference: Registers) - # for more info on display control registers - # https://01.org/linuxgraphics/documentation/hardware-specification-prms - #+-----------------------------+---------------------------------------+-----+ - #| Intel docs | devicetree.cb | eDP | - #+-----------------------------+---------------------------------------+-----+ - #| Power up delay | `gpu_panel_power_up_delay` | T3 | - #+-----------------------------+---------------------------------------+-----+ - #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | - #+-----------------------------+---------------------------------------+-----+ - #| Power Down delay | `gpu_panel_power_down_delay` | T10 | - #+-----------------------------+---------------------------------------+-----+ - #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | - #+-----------------------------+---------------------------------------+-----+ - #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | - #+-----------------------------+---------------------------------------+-----+ - device ref igpu on - register "panel_cfg" = "{ - .up_delay_ms = 200, - .down_delay_ms = 50, - .cycle_delay_ms = 500, - .backlight_on_delay_ms = 1, - .backlight_off_delay_ms = 200, - .backlight_pwm_hz = 200, - }" - end + device ref igpu on end device ref dtt on end device ref tbt_pcie_rp0 on end device ref tbt_pcie_rp1 on end |