diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-09-10 00:21:23 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-09-11 18:51:59 +0000 |
| commit | 3d469fad97f962abb61b5a70837ef96b2c4a78cb (patch) | |
| tree | e7b8059e1fa80bf4a3cdfad675e237de6824b92f /src/mainboard/google/brya/variants/baseboard | |
| parent | e5cf666b9a5fa60d1253a94fc1e62c8ba86f28ce (diff) | |
mb/google/brya: Replace white space with tab
This patch unifies line indentation.
Change-Id: Ieeb580057d8abb20afe3a5d73f5f835e6d31c899
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb | 24 |
2 files changed, 14 insertions, 14 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index cc6664cd74..3b9acea22b 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -11,8 +11,8 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # S0ix enable - register "s0ix_enable" = "1" + # S0ix enable + register "s0ix_enable" = "1" # DPTF enable register "dptf_enable" = "1" diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 52651090f7..6f55770d2b 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -13,8 +13,8 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - # S0ix enable - register "s0ix_enable" = "1" + # S0ix enable + register "s0ix_enable" = "1" # DPTF enable register "dptf_enable" = "1" @@ -85,33 +85,33 @@ chip soc/intel/alderlake .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[1] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[2] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 900, - .fall_time_ns = 400, - .data_hold_time_ns = 50, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[3] = { .early_init = 1, .speed = I2C_SPEED_FAST, .rise_time_ns = 600, - .fall_time_ns = 400, - .data_hold_time_ns = 50, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, .i2c[5] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 650, - .fall_time_ns = 400, - .data_hold_time_ns = 50, + .fall_time_ns = 400, + .data_hold_time_ns = 50, }, }" |