diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2021-05-03 22:46:34 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-13 20:22:41 +0000 |
| commit | 0d37fcb0040ab27ce8a3ee59224aa3389e5f57b4 (patch) | |
| tree | 72888a5da0daad79e52cb0219f7dae3e111271df /src/mainboard/google/brya/variants/baseboard | |
| parent | 880ac43a85b7e16d4fda065f61b6e04a57d11b3c (diff) | |
mb/google/brya: enable DPTF functionality for brya
Enable DPTF functionality for Alder Lake based brya
BRANCH=None
BUG=b:188028732
TEST=Built and tested on brya board
Change-Id: I33266c85aa30869466034ccbab04a3c7820ae2b0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb index e7a6ed3994..16678cb816 100644 --- a/src/mainboard/google/brya/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -17,6 +17,14 @@ chip soc/intel/alderlake # S0ix enable register "s0ix_enable" = "1" + # DPTF enable + register "dptf_enable" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 15, + .tdp_pl2_override = 55, + }" + # This disabled autonomous GPIO power management, otherwise # old cr50 FW only supports short pulses; need to clarify # the minimum PCH IRQ pulse width with Intel, b/180111628 |