mb/google/brask: Add more gpios to lock

Add rest of soc sensitive gpios to lock for brask.

BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brask boots successfully to kernel.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 40 insertions, 40 deletions

diff --git a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
index 5383aa7b0c..ed0416b022 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
+++ b/src/mainboard/google/brya/variants/baseboard/brask/gpio.c
@@ -35,7 +35,7 @@ static const struct pad_config gpio_table[] = {
 	/* A15 : USB_OC2# ==> USB_C2_OC_ODL */
 	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
 	/* A16 : USB_OC3# ==> USB_A0_OC_ODL */
-	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG),
 	/* A17 : DISP_MISCC ==> NC */
 	PAD_NC(GPP_A17, NONE),
 	/* A18 : DDSP_HPDB ==> HDMI_HPD */
@@ -58,17 +58,17 @@ static const struct pad_config gpio_table[] = {
 	/* B2  : VRALERT# ==> M2_SSD_PLA_L */
 	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
 	/* B3  : PROC_GP2 ==> NC */
-	PAD_NC(GPP_B3, NONE),
+	PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
 	/* B4  : PROC_GP3 ==> SSD_PERST_L */
-	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
 	/* B5  : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */
-	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
 	/* B6  : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */
-	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
 	/* B7  : ISH_12C1_SDA ==> NC */
-	PAD_NC(GPP_B7, NONE),
+	PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
 	/* B8  : ISH_I2C1_SCL ==> NC */
-	PAD_NC(GPP_B8, NONE),
+	PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
 	/* B9  : NC */
 	PAD_NC(GPP_B9, NONE),
 	/* B10 : NC */
@@ -80,13 +80,13 @@ static const struct pad_config gpio_table[] = {
 	/* B13 : PLTRST# ==> PLT_RST_L */
 	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
 	/* B14 : SPKR ==> PWM_PP3300_BUZZER */
-	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
+	PAD_CFG_NF_LOCK(GPP_B14, NONE, NF1, LOCK_CONFIG),
 	/* B15 : TIME_SYNC0 ==> TP159 */
-	PAD_NC(GPP_B15, NONE),
+	PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
 	/* B16 : I2C5_SDA ==> NC */
-	PAD_NC(GPP_B16, NONE),
+	PAD_NC_LOCK(GPP_B16, NONE, LOCK_CONFIG),
 	/* B17 : I2C5_SCL ==> NC */
-	PAD_NC(GPP_B17, NONE),
+	PAD_NC_LOCK(GPP_B17, NONE, LOCK_CONFIG),
 	/* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
 	PAD_NC(GPP_B18, NONE),
 	/* B19 : NC */
@@ -118,13 +118,13 @@ static const struct pad_config gpio_table[] = {
 	PAD_NC(GPP_C7, NONE),
 
 	/* D0  : ISH_GP0 ==> PCH_FP_BOOT0 */
-	PAD_NC(GPP_D0, NONE),
+	PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
 	/* D1  : ISH_GP1 ==> FP_RST_ODL */
-	PAD_CFG_GPO(GPP_D1, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
 	/* D2  : ISH_GP2 ==> EN_FP_PWR */
-	PAD_CFG_GPO(GPP_D2, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG),
 	/* D3  : ISH_GP3 ==> EN_NFC_PWR */
-	PAD_CFG_GPO(GPP_D3, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG),
 	/* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
 	PAD_CFG_GPO(GPP_D4, 1, DEEP),
 	/* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
@@ -136,34 +136,34 @@ static const struct pad_config gpio_table[] = {
 	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
 	/* D9  : ISH_SPI_CS# ==> USB_C2_LSX_TX */
-	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4),
+	PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG),
 	/* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
-	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4),
+	PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG),
 	/* D11 : ISH_SPI_MISO ==> DDIA_DP_CTRLCLK */
-	PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_D11, NONE, NF2, LOCK_CONFIG),
 	/* D12 : ISH_SPI_MOSI ==> DDIA_DP_CTRLDATA */
-	PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2),
+	PAD_CFG_NF_LOCK(GPP_D12, NONE, NF2, LOCK_CONFIG),
 	/* D13 : ISH_UART0_RXD ==> TP97 */
-	PAD_NC(GPP_D13, NONE),
+	PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
 	/* D14 : ISH_UART0_TXD ==> TP93 */
-	PAD_NC(GPP_D14, NONE),
+	PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
 	/* D15 : ISH_UART0_RTS# ==> NC */
-	PAD_NC(GPP_D15, NONE),
+	PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
 	/* D16 : ISH_UART0_CTS# ==> NC */
-	PAD_NC(GPP_D16, NONE),
+	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 	/* D17 : UART1_RXD ==> SD_PE_PRSNT_L */
-	PAD_CFG_GPI(GPP_D17, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
 	/* D18 : UART1_TXD ==> SD_PE_RST_L */
-	PAD_CFG_GPO(GPP_D18, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG),
 	/* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
 	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 
 	/* E0  : SATAXPCIE0 ==> CLKREQ_9 */
 	PAD_NC(GPP_E0, NONE),
 	/* E1  : THC0_SPI1_IO2 ==> NC */
-	PAD_NC(GPP_E1, NONE),
+	PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG),
 	/* E2  : THC0_SPI1_IO3 ==> NC */
-	PAD_NC(GPP_E2, NONE),
+	PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG),
 	/* E3  : PROC_GP0 ==> TP94644 */
 	PAD_NC(GPP_E3, NONE),
 	/* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
@@ -171,21 +171,21 @@ static const struct pad_config gpio_table[] = {
 	/* E5  : SATA_DEVSLP1 ==> NC */
 	PAD_NC(GPP_E5, NONE),
 	/* E6  : THC0_SPI1_RST# ==> GPPE6_STRAP */
-	PAD_NC(GPP_E6, NONE),
+	PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
 	/* E7  : PROC_GP1 ==> TP94643 */
 	PAD_NC(GPP_E7, NONE),
 	/* E8  : SLP_DRAM# ==> WIFI_DISABLE_L */
 	PAD_CFG_GPO(GPP_E8, 1, DEEP),
 	/* E9  : USB_OC0# ==> USB_C0_OC_ODL */
-	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG),
 	/* E10 : THC0_SPI1_CS# ==> NC */
-	PAD_NC(GPP_E10, NONE),
+	PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 	/* E11 : THC0_SPI1_CLK ==> NC */
-	PAD_NC(GPP_E11, NONE),
+	PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 	/* E12 : THC0_SPI1_IO1 ==> NC */
-	PAD_NC(GPP_E12, NONE),
+	PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG),
 	/* E13 : THC0_SPI1_IO2 ==> NC */
-	PAD_NC(GPP_E13, NONE),
+	PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 	/* E14 : DDSP_HPDA ==> SOC_DP_HPD */
 	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 	/* E15 : RSVD_TP ==> PCH_WP_OD */
@@ -193,7 +193,7 @@ static const struct pad_config gpio_table[] = {
 	/* E16 : RSVD_TP ==> CLKREQ_8 */
 	PAD_NC(GPP_E16, NONE),
 	/* E17 : THC0_SPI1_INT# ==> TP102 */
-	PAD_NC(GPP_E17, NONE),
+	PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 	/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_TX */
 	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
 	/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_RX_STRAP */
@@ -236,15 +236,15 @@ static const struct pad_config gpio_table[] = {
 	/* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */
 	PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG),
 	/* F14 : GSXDIN ==> EN_PP3300_SSD */
-	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_F14, 1, LOCK_CONFIG),
 	/* F15 : GSXSRESET# ==> FPMCU_INT_L */
 	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
 	PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
 	/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
-	PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT),
+	PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG),
 	/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
-	PAD_CFG_GPI(GPP_F18, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
 	/* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */
 	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 	/* F20 : EXT_PWR_GATE# ==> TP94669 */
@@ -263,7 +263,7 @@ static const struct pad_config gpio_table[] = {
 	/* H2  : GPPH2_BOOT_STRAP3 */
 	PAD_NC(GPP_H2, NONE),
 	/* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
-	PAD_CFG_GPI(GPP_H3, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG),
 	/* H4  : I2C0_SDA ==> PCH_I2C_AUD_SDA */
 	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 	/* H5  : I2C0_SCL ==> PCH_I2C_AUD_SCL */
@@ -281,9 +281,9 @@ static const struct pad_config gpio_table[] = {
 	/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 	/* H12 : I2C7_SDA ==> SD_PE_WAKE_ODL */
-	PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+	PAD_CFG_GPI_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 	/* H13 : I2C7_SCL ==> EN_PP3300_SD */
-	PAD_CFG_GPO(GPP_H13, 1, DEEP),
+	PAD_CFG_GPO_LOCK(GPP_H13, 1, LOCK_CONFIG),
 	/* H14 : NC */
 	PAD_NC(GPP_H14, NONE),
 	/* H15 : DDPB_CTRLCLK ==> DDIB_HDMI_CTRLCLK */