diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2021-10-22 10:59:41 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-11-02 08:14:05 +0000 |
| commit | d6798e96fcb3206ba68ee49173356ab2bd032eeb (patch) | |
| tree | ff929357953ee259436887768f34c418ead263d1 /src/mainboard/google/brya/variants/baseboard/brask | |
| parent | fec936659ccb880278bd67fa154897a5b223f7cc (diff) | |
mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this
mainboard and are not routed either, so remove them from the devicetree
completely. PCIe root port #7 (00:1c.6) is connected and used. Add the
missing settings for L1 substates and latency reporting to disable these
features for this port as well.
Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard/brask')
0 files changed, 0 insertions, 0 deletions