diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-02-08 13:03:25 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-03-07 19:11:57 +0000 |
| commit | c0d7d6b564e979b29fab50203b53fdb4722920c9 (patch) | |
| tree | 74dbf8a913f76c880c44c9040055ad779f90d6c1 /src/mainboard/google/brya/variants/baseboard/brask | |
| parent | 1e50dfbcded1c2e90262a390511a145b38c47b7c (diff) | |
mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.
BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard/brask')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index 98dd3a5fec..9eb8bb2adb 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -76,16 +76,6 @@ chip soc/intel/alderlake # FIVR RFI Spread Spectrum 1.5% register "FivrSpreadSpectrum" = "FIVR_SS_1_5" - # This disables autonomous GPIO power management, otherwise - # old cr50 FW only supports short pulses. - register "gpio_override_pm" = "1" - register "gpio_pm[COMM_0]" = "0" - register "gpio_pm[COMM_1]" = "0" - register "gpio_pm[COMM_2]" = "0" - register "gpio_pm[COMM_3]" = "0" - register "gpio_pm[COMM_4]" = "0" - register "gpio_pm[COMM_5]" = "0" - # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |