diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-06 08:35:56 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-12 03:56:14 +0000 |
| commit | a52b9c3a40dd082213b419f62d6ae3e1e071363b (patch) | |
| tree | 96ecf55c2913b66d85498dbe4b941d0c6f048e93 /src/mainboard/google/brya/variants/baseboard/brask | |
| parent | bf4592743c6b90c60a71842630e426a03b334e11 (diff) | |
mb/google/brya: Move gpio_pm settings for brya variants to baseboards
The factory versions (minor version 22) of cr50 FW have an issue with
producing short interrupt pulses, which can be missed by the ADL PCH
if autonomous GPIO power management is enabled, therefore instead of
continually adding the setting to all the variants, move it to the
baseboard instead.
Change-Id: I337f1e9e8f958c02bb73e6701a06c0b88a4757d7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/google/brya/variants/baseboard/brask')
| -rw-r--r-- | src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index d9a4e42c04..a7328a9bbe 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -71,6 +71,16 @@ chip soc/intel/alderlake # FIVR RFI Spread Spectrum 1.5% register "FivrSpreadSpectrum" = "FIVR_SS_1_5" + # This disables autonomous GPIO power management, otherwise + # old cr50 FW only supports short pulses. + register "gpio_override_pm" = "1" + register "gpio_pm[COMM_0]" = "0" + register "gpio_pm[COMM_1]" = "0" + register "gpio_pm[COMM_2]" = "0" + register "gpio_pm[COMM_3]" = "0" + register "gpio_pm[COMM_4]" = "0" + register "gpio_pm[COMM_5]" = "0" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | |