mb/google/brya: Enable DDR4 SODIMM for brask

Enable SMBus to support DDR4 SODIMM for brask. Enable 'smbus' in
brask device tree and add SPD addressese for the two DIMMs.

Separate the Kconfig items of brya and brask. Move
HAVE_SPD_IN_CBFS and CHROMEOS_DRAM_PART_NUMBER_IN_CBI to brya
and add config SPD_CACHE_IN_FMAP to brask.

Add a new section RW_SPD_CACHE to fmd for caching SPD data.

The renamed romstage.c is used by both brya and brask and a new
function variant_get_spd_info is provided to support the different
SPD source types.

BUG=b:194055762
BRANCH=None
TEST=build pass

Change-Id: I41c57a3df127356b8c7e619c4d6144dc73aeac72
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

3 files changed, 45 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
index 6c29346470..1693d2e263 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
+++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
@@ -1,5 +1,6 @@
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 3b9acea22b..646309ecd7 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -149,5 +149,6 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref hda on end
+		device ref smbus on end
 	end
 end
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/memory.c b/src/mainboard/google/brya/variants/baseboard/brask/memory.c
new file mode 100644
index 0000000000..2e24110bb1
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/brask/memory.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = 1,
+	},
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &ddr4_mem_config;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
+}