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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-16 11:17:07 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-12-20 17:47:24 +0000
commita7e85d43c858f063a9179c7865aef6ee32158c49 (patch)
tree55eea940a2fe4e0631e8f54794a348e15ad162d2 /src/mainboard/google/brya/variants/anahera
parent814069174279b02f63660cbff6a002904049828a (diff)
mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetrees
None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/variants/anahera')
-rw-r--r--src/mainboard/google/brya/variants/anahera/overridetree.cb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index dc563a4c61..118ce0c41f 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -215,6 +215,7 @@ chip soc/intel/alderlake
register "stop_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
register "has_power_resource" = "1"
+ register "disable_gpio_export_in_crs" = "1"
device i2c 10 on end
end
chip drivers/i2c/hid
@@ -229,6 +230,7 @@ chip soc/intel/alderlake
"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
register "generic.enable_delay_ms" = "1"
register "generic.has_power_resource" = "1"
+ register "generic.disable_gpio_export_in_crs" = "1"
register "hid_desc_reg_offset" = "0x01"
device i2c 40 on end
end