mb/google/brya: Implement SLP_S0_GATE signal

The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to
provide an indication to the rest of the platform when the system is
entering its software-initiated low-power state (i.e. S0ix). This lets
the platform distinguish between opportunistic S0ix entry and the runtime
suspend mechanism.

BUG=b:180401723
TEST=abuild

Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 24 insertions, 0 deletions

diff --git a/src/mainboard/google/brya/mainboard.asl b/src/mainboard/google/brya/mainboard.asl
new file mode 100644
index 0000000000..c60db3081c
--- /dev/null
+++ b/src/mainboard/google/brya/mainboard.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/*
+		 * On S0ix entry, clear the SLP_S0_GATE pin, so that the rest of
+		 * the platform can transition to its low power state as well.
+		 */
+		\_SB.PCI0.CTXS(GPIO_SLP_S0_GATE);
+	} Else {
+		/*
+		 * On S0ix exit, set the SLP_S0_GATE pin, so that the rest of
+		 * the platform will resume from its low power state.
+		 */
+		\_SB.PCI0.STXS(GPIO_SLP_S0_GATE);
+	}
+}