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author | Angel Pons <th3fanbus@gmail.com> | 2021-04-19 22:31:49 +0200 |
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committer | Angel Pons <th3fanbus@gmail.com> | 2021-06-14 09:59:40 +0000 |
commit | 68d8357dab55660058ad1ab8dca34fd03e0adbb5 (patch) | |
tree | 2dc32faf914baa992e67d8af7f7868422c16a046 /src/mainboard/google/brya/chromeos.c | |
parent | 07baa7a7f06369d9dc795c5a9b34314e88d14dd8 (diff) |
soc/intel/broadwell/pch: Replace ACPI device NVS
The same functionality can be provided through a runtime-generated SSDT.
The remaining parts of device NVS are removed in a follow-up.
Since the SSDTs are only loaded after the DSDT (if loaded at all), using
SSDT-provided objects outside method bodies is not possible: the objects
are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing
to this, the operation regions used by the _PS0 and _PS3 methods need to
be moved into the SSDT, as they depend on the SSDT-provided BAR1 values.
Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with
no errors and contains expected values. Linux does not complain either.
Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/brya/chromeos.c')
0 files changed, 0 insertions, 0 deletions