diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-08-16 14:22:25 -0600 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-18 18:28:04 +0000 |
| commit | e0ddb37ae806995fd6cd830b6c22c364ac2f425e (patch) | |
| tree | 1e96e3898b66b5890568c776c065b7e44c4e7f0d /src/mainboard/google/brya/acpi/nbci.asl | |
| parent | bcc3059d83b7503a3247690a895a05127102d414 (diff) | |
mb/google/brya/acpi: Add PCIe SRCCLK# control to RTD3 methods
This patch adds support for turning the PCIe SRCCLK# on and off during
RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver).
TEST=GC6 and GCOFF sequences still work
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/google/brya/acpi/nbci.asl')
0 files changed, 0 insertions, 0 deletions