diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2024-09-09 21:29:07 -0600 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2024-09-12 17:27:57 +0000 |
| commit | 192a140843e1699f14ab09e9154a29227018f210 (patch) | |
| tree | 34e68af015b19c6b333c21f05814ff165d41270e /src/mainboard/google/brox | |
| parent | b46bd95ccdec355d446b3fd49ace89710cb4d6f2 (diff) | |
mb/google/brox/var/brox: Enable ASPM for PCIe4 SSD of CPU
Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.
BUG=b:363854853
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I386f8e88a5af661b1f4c04d2e2a34cd181608bd8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
Diffstat (limited to 'src/mainboard/google/brox')
| -rw-r--r-- | src/mainboard/google/brox/variants/brox/overridetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index f2342f03c5..79771eb2db 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -273,6 +273,7 @@ chip soc/intel/alderlake .clk_req = 3, .clk_src = 3, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1 }" probe STORAGE STORAGE_NVME probe unprovisioned |