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authorAshish Kumar Mishra <ashish.k.mishra@intel.com>2024-02-02 20:18:56 +0530
committerShelley Chen <shchen@google.com>2024-02-08 06:02:54 +0000
commit32ebaef73c8e1cc367e1c63af587250041fce32a (patch)
treecb21b257f38e60eadf225773379ed1384fb1a52b /src/mainboard/google/brox/variants
parent33659d246e5d89885413d4ea30525dacdacc56ee (diff)
mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE
In case where PAD_CFG_GPI_INT() is initialized with a pin value lower to PAD_CFG_GPI_IRQ_WAKE() for same GPIO community the set_ioapic_used() is only called for the PAD_CFG_GPI_IRQ_WAKE() pin. Due to this the IRQ associated with PAD_CFG_GPI_INT() is found free by find_free_unique_irq() during IRQ assignment and assigned to other pins which causes IRQ conflicts BUG=b:322984217 BRANCH=None TEST=Boot test on brox, check if correct IRQ assigned to EC Change-Id: I8c3d557e888b8d0ceac203f49b702910fba26d6d Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80334 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/google/brox/variants')
-rw-r--r--src/mainboard/google/brox/variants/baseboard/brox/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
index 5432bd1143..3f39f1813f 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
+++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c
@@ -140,7 +140,7 @@ static const struct pad_config gpio_table[] = {
PAD_NC(GPP_C7, NONE),
/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */
- PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, LEVEL),
+ PAD_CFG_GPI_INT_SWAPPED(GPP_D0, NONE, PLTRST, LEVEL),
/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT),
/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */