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authorRen Kuo <ren.kuo@quanta.corp-partner.google.com>2024-10-07 16:42:54 +0800
committerSubrata Banik <subratabanik@google.com>2024-10-21 05:58:30 +0000
commit4ef7c4602bf30fe898bdad28f47d44492776766e (patch)
tree07ac40f367dde6004ebde75625b31cbd6fe0e993 /src/mainboard/google/brox/variants/jubilant/gpio.c
parent69ab3b8f684fdca673501167c4120d5efdea85d7 (diff)
mb/google/brox/jubilant: Modify WWAN Rolling RW101R-GL power sequence
There is no ACPI power resource for LTE module Rolling RW101R-GL, therefore implement the power sequence of power-on, power-off, and reset timing from GPIO init, bootstate init callbacks, and smihandler function. BUG=b:368450447 BRANCH=None TEST= Build firmware and verify on jubilant with LTE:RW101R-GL. Measure the power on, power off, and reset timing. Run warm boot, cold boot and suspend/resume to make sure WWAN devcie is workable. Change-Id: I4a205e3db777c7c225d31b6cc802883fd7167089 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/google/brox/variants/jubilant/gpio.c')
-rw-r--r--src/mainboard/google/brox/variants/jubilant/gpio.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mainboard/google/brox/variants/jubilant/gpio.c b/src/mainboard/google/brox/variants/jubilant/gpio.c
index 71c00eadd0..c633a9116c 100644
--- a/src/mainboard/google/brox/variants/jubilant/gpio.c
+++ b/src/mainboard/google/brox/variants/jubilant/gpio.c
@@ -28,9 +28,10 @@ static const struct pad_config override_gpio_table[] = {
*/
PAD_CFG_GPO_LOCK(GPP_A12, 1, LOCK_CONFIG),
/* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */
- PAD_CFG_GPO_LOCK(GPP_H23, 1, LOCK_CONFIG),
+ PAD_CFG_GPO_LOCK(GPP_H23, 0, LOCK_CONFIG),
/* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */
- PAD_CFG_GPO_LOCK(GPP_F21, 1, LOCK_CONFIG),
+ PAD_CFG_GPO_LOCK(GPP_F21, 0, LOCK_CONFIG),
+
/* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L */
PAD_CFG_GPI_APIC_LOCK(GPP_H19, NONE, LEVEL, NONE, LOCK_CONFIG),
@@ -193,7 +194,7 @@ static const struct pad_config romstage_gpio_table[] = {
/* GPP_H23 : SRCCLKREQ5_L ==> WWAN_RST_L */
PAD_CFG_GPO_LOCK(GPP_H23, 0, LOCK_CONFIG),
/* GPP_F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_FCPO_L */
- PAD_CFG_GPO_LOCK(GPP_F21, 1, LOCK_CONFIG),
+ PAD_CFG_GPO_LOCK(GPP_F21, 0, LOCK_CONFIG),
/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
PAD_CFG_GPI(GPP_E15, NONE, PLTRST),