mb/google/brox: Create new Brox baseboard

This CL is just getting the initial brox framework to get the
baseboard building.  Copied files from brask baseboard and tried to
remove contents of some files like the device tree and memory IDs.
Added support for memory part "MT62F512M32D2DR-031 WT:B", mapped to
DRAM ID 0.

BUG=b:300690448
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_BROX -x -a

Change-Id: I929b465646ac4c69d4bab33ce23848c7b1fa0f98
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

1 files changed, 90 insertions, 0 deletions

diff --git a/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..ad8eb05833
--- /dev/null
+++ b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <chip.h>
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stdint.h>
+
+/* The next set of functions return the gpio table and fill in the number of entries for
+ * each table.
+ */
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_gpio_override_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_romstage_gpio_table(size_t *num);
+void fw_config_gpio_padbased_override(struct pad_config *padbased_table);
+
+const struct mb_cfg *variant_memory_params(void);
+void variant_get_spd_info(struct mem_spd *spd_info);
+int variant_memory_sku(void);
+bool variant_is_half_populated(void);
+void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);
+void variant_fill_ssdt(const struct device *dev);
+void variant_configure_pads(void);
+
+enum s0ix_entry {
+	S0IX_EXIT,
+	S0IX_ENTRY,
+};
+
+void variant_generate_s0ix_hook(enum s0ix_entry entry);
+
+/* Modify devictree settings during ramstage */
+void variant_devtree_update(void);
+
+void variant_update_descriptor(void);
+
+struct cpu_power_limits {
+	uint16_t mchid;
+	u8 cpu_tdp;
+	unsigned int pl1_min_power;
+	unsigned int pl1_max_power;
+	unsigned int pl2_min_power;
+	unsigned int pl2_max_power;
+	unsigned int pl4_power;
+};
+
+struct system_power_limits {
+	uint16_t mchid;
+	u8 cpu_tdp;
+	/* PsysPL2 in Watts */
+	unsigned int psys_pl2_power;
+};
+
+struct psys_config {
+	/*
+	 * The efficiency of type-c chargers
+	 * For example, 'efficiency = 97' means setting 97% of max power to account for
+	 * cable loss and FET Rdson loss in the path from the source.
+	 */
+	unsigned int efficiency;
+
+	/* The maximum current maps to the Psys signal */
+	unsigned int psys_imax_ma;
+
+	/* The voltage of barrel jack */
+	unsigned int bj_volts_mv;
+};
+
+/* Modify Power Limit devictree settings during ramstage */
+void variant_update_power_limits(const struct cpu_power_limits *limits,
+				 size_t num_entries);
+
+
+/*
+ * Modify Power Limit and PsysPL devictree settings during ramstage.
+ * Note, this function must be called in front of calling variant_update_power_limits.
+ */
+void variant_update_psys_power_limits(const struct cpu_power_limits *limits,
+					const struct system_power_limits *sys_limits,
+					size_t num_entries,
+					const struct psys_config *config);
+
+void variant_init(void);
+void variant_finalize(void);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */