diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-07-26 11:48:06 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-27 21:25:06 +0200 |
| commit | 139314bffd5ff29847661c536130d8d8d3e261bf (patch) | |
| tree | 964701ca27fcf8ad741641b984c797986d60d261 /src/mainboard/google/bolt/dsdt.asl | |
| parent | 60cc75df83f2da64132b6da6dd431417da6b2f4e (diff) | |
mainboard/google/bolt: remove unobtainable mainboard
The bolt board was a proof of concept device that has never
made it out in the wild. Moreover, I don't think any of these
boards exist any longer.
Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15901
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/google/bolt/dsdt.asl')
| -rw-r--r-- | src/mainboard/google/bolt/dsdt.asl | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/src/mainboard/google/bolt/dsdt.asl b/src/mainboard/google/bolt/dsdt.asl deleted file mode 100644 index 9e5a114938..0000000000 --- a/src/mainboard/google/bolt/dsdt.asl +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2012 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define ENABLE_TPM - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - #include "acpi/mainboard.asl" - - // global NVS and variables - #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - // CPU - #include <cpu/intel/haswell/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - - #include <drivers/intel/gma/acpi/default_brightness_levels.asl> - } - } - - // Thermal handler - #include "acpi/thermal.asl" - - // Chrome OS specific - #include "acpi/chromeos.asl" - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - // Chipset specific sleep states - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> -} |