diff options
| author | Sridahr Siricilla <sridhar.siricilla@intel.com> | 2021-09-17 22:25:17 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-07-14 23:12:36 +0000 |
| commit | 096ce1444ec7fa204f331a75c2ac9d00ea00bf12 (patch) | |
| tree | a14079aed4bda3bb5a6ae64308ca7c8f43b488ff /src/mainboard/google/beltino | |
| parent | 1dc080fc1d812628b80529441c52a5ee571340ed (diff) | |
soc/intel/alderlake: Support PCIe hardware compliance test mode
The validation process verifies that hardware components comply with
the standard hardware specifications. For instance, PCI express
implementation must comply with the hardware PCIe specification
requirements: Electrical, Configuration, Link Protocol and Transaction
Protocol. To perform these tests the hardware must be configured in a
particular state: some feature related to power management need to be
turned off, hot plug should be enabled...
This patch sets the appropriate FSP Updateable Product Data flags to
get the hardware in the proper configuration:
- Enable PCIe hotplug on all ports
- Set clock sources to run free
- Set the FSP compliance test mode flag
BUG=b:235863379
TEST=Compilation with and without the flag
Verify code path with instrumentation
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic07b9276121dfbd273a8f63a1f775ddbd3566884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/google/beltino')
0 files changed, 0 insertions, 0 deletions