Add/Combine Broadwell Chromebooks using variant board scheme

Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.

Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]

Additionally, some minor cleanup/changes were made:
 - I2C devices set to use level (vs edge) interrupt triggering
 - HDA verb entries use simplified macro entry format
 - correct FADT table header version
 - remove unused ACPI device entries / .asl file(s)
 - clean up ACPI code (e.g., trackpad on Lulu)
 - adjust _CID for trackpad on Lulu in order to not load non-functional
    Windows driver (does not affect Linux)
 - remove unused header includes (multiple/various)
 - correct I2C addresses used for SMBIOS device entries
 - correct misc typos etc

The existing auron_paine samus boards are removed.

Variant setup modeled after google/slippy

Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 0 insertions, 53 deletions

diff --git a/src/mainboard/google/auron_paine/chromeos.c b/src/mainboard/google/auron_paine/chromeos.c
deleted file mode 100644
index 61b3e4ef1e..0000000000
--- a/src/mainboard/google/auron_paine/chromeos.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <string.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/gpio.h>
-
-/* SPI Write protect is GPIO 16 */
-#define CROS_WP_GPIO	58
-
-#ifndef __PRE_RAM__
-#include <boot/coreboot_tables.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-	struct lb_gpio chromeos_gpios[] = {
-		{CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"},
-		{-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
-		{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
-		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
-		{-1, ACTIVE_HIGH, 0, "power"},
-		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
-	};
-	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
-}
-#endif
-
-int get_write_protect_state(void)
-{
-	return get_gpio(CROS_WP_GPIO);
-}
-
-static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
-	CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
-};
-
-void mainboard_chromeos_acpi_generate(void)
-{
-	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
-}