diff options
author | Georg Wicherski <gwicherski@gmail.com> | 2015-10-15 12:58:04 +0200 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2016-03-10 16:54:39 +0100 |
commit | 422bf6b47226d68005003c17753fd30685e244c6 (patch) | |
tree | c83c1bc7696cdbe974857d5150085869c99d506e /src/mainboard/google/auron_paine/acpi/superio.asl | |
parent | 1eb1e3b8bf75984ad0d5b00fc34706f0e8391503 (diff) |
mainboards/google/auron_paine: add new port
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine
code originally from commit bd61dfd in Google branch
firmware-paine-6301.58.B .
Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: https://review.coreboot.org/11907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/google/auron_paine/acpi/superio.asl')
-rw-r--r-- | src/mainboard/google/auron_paine/acpi/superio.asl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/mainboard/google/auron_paine/acpi/superio.asl b/src/mainboard/google/auron_paine/acpi/superio.asl new file mode 100644 index 0000000000..07d6b23e53 --- /dev/null +++ b/src/mainboard/google/auron_paine/acpi/superio.asl @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include <mainboard/google/auron_paine/ec.h> + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1 + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl> |