google/auron: Add mainboard

Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit:  d20a1d1a22d64546a5d8761b18ab29732ec0b848

Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

7 files changed, 303 insertions, 0 deletions

diff --git a/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex b/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex
new file mode 100644
index 0000000000..eb41f0bfb1
--- /dev/null
+++ b/src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex
@@ -0,0 +1,17 @@
+# Elpida EDJ4216EFBG-GN-F
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE
+45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46
+00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex b/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex
new file mode 100644
index 0000000000..7b0932743d
--- /dev/null
+++ b/src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6AFR6A-PBA
+92 12 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 FF AB
+48 4D 54 34 32 35 53 36 41 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/spd/Makefile.inc b/src/mainboard/google/auron/spd/Makefile.inc
new file mode 100644
index 0000000000..7b0292d826
--- /dev/null
+++ b/src/mainboard/google/auron/spd/Makefile.inc
@@ -0,0 +1,54 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+
+romstage-y += spd.c
+
+SPD_BIN = $(obj)/spd.bin
+
+# { GPIO47, GPIO9, GPIO13 }
+SPD_SOURCES  = Micron_4KTF25664HZ       # 0b0000
+SPD_SOURCES += Hynix_HMT425S6AFR6A      # 0b0001
+SPD_SOURCES += Elpida_EDJ4216EFBG       # 0b0010
+SPD_SOURCES += Micron_4KTF25664HZ       # 0b0011
+SPD_SOURCES += Micron_4KTF25664HZ       # 0b0100
+SPD_SOURCES += Hynix_HMT425S6AFR6A      # 0b0101
+SPD_SOURCES += Elpida_EDJ4216EFBG       # 0b0110
+SPD_SOURCES += empty                    # 0b0111
+SPD_SOURCES += empty                    # 0b1000
+SPD_SOURCES += empty                    # 0b1001
+SPD_SOURCES += empty                    # 0b1010
+SPD_SOURCES += empty                    # 0b1011
+SPD_SOURCES += empty                    # 0b1100
+SPD_SOURCES += empty                    # 0b1101
+SPD_SOURCES += empty                    # 0b1110
+SPD_SOURCES += empty                    # 0b1111
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+	for f in $+; \
+	  do for c in $$(cat $$f | grep -v ^#); \
+	    do echo -e -n "\\x$$c"; \
+	  done; \
+	done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab
diff --git a/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex b/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex
new file mode 100644
index 0000000000..cbe9e4fbfe
--- /dev/null
+++ b/src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex
@@ -0,0 +1,17 @@
+# Micron 4KTF25664HZ-1G6E1
+92 11 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2C 00 00 00 00 00 00 00 AD 75
+34 4B 54 46 32 35 36 36 34 48 5A 2D 31 47 36 45
+31 20 45 31 80 2C 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/auron/spd/empty.spd.hex b/src/mainboard/google/auron/spd/empty.spd.hex
new file mode 100644
index 0000000000..9ec39f1ba4
--- /dev/null
+++ b/src/mainboard/google/auron/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/auron/spd/spd.c b/src/mainboard/google/auron/spd/spd.c
new file mode 100644
index 0000000000..2f3f20c2e2
--- /dev/null
+++ b/src/mainboard/google/auron/spd/spd.c
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <cbfs.h>
+#include <console/console.h>
+#include <endian.h>
+#include <string.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <mainboard/google/auron/ec.h>
+#include <mainboard/google/auron/gpio.h>
+#include <mainboard/google/auron/spd/spd.h>
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+	const int spd_banks[8] = {  8, 16, 32, 64, -1, -1, -1, -1 };
+	const int spd_capmb[8] = {  1,  2,  4,  8, 16, 32, 64,  0 };
+	const int spd_rows[8]  = { 12, 13, 14, 15, 16, -1, -1, -1 };
+	const int spd_cols[8]  = {  9, 10, 11, 12, -1, -1, -1, -1 };
+	const int spd_ranks[8] = {  1,  2,  3,  4, -1, -1, -1, -1 };
+	const int spd_devw[8]  = {  4,  8, 16, 32, -1, -1, -1, -1 };
+	const int spd_busw[8]  = {  8, 16, 32, 64, -1, -1, -1, -1 };
+	char spd_name[SPD_PART_LEN+1] = { 0 };
+
+	int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+	int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+	int rows  = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+	int cols  = spd_cols[spd[SPD_ADDRESSING] & 7];
+	int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+	int devw  = spd_devw[spd[SPD_ORGANIZATION] & 7];
+	int busw  = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+	/* Module type */
+	printk(BIOS_INFO, "SPD: module type is ");
+	switch (spd[SPD_DRAM_TYPE]) {
+	case SPD_DRAM_DDR3:
+		printk(BIOS_INFO, "DDR3\n");
+		break;
+	case SPD_DRAM_LPDDR3:
+		printk(BIOS_INFO, "LPDDR3\n");
+		break;
+	default:
+		printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+		break;
+	}
+
+	/* Module Part Number */
+	memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+	spd_name[SPD_PART_LEN] = 0;
+	printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+	printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, "
+	       , banks, ranks, rows, cols);
+	printk(BIOS_INFO, "density %d Mb\n", capmb);
+
+	printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+	       devw, busw);
+
+	if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+		/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+		printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+		       capmb / 8 * busw / devw * ranks);
+	}
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+	int spd_bits[3] = {
+		SPD_GPIO_BIT0,
+		SPD_GPIO_BIT1,
+		SPD_GPIO_BIT2
+	};
+	int spd_gpio[3];
+	int spd_index;
+	size_t spd_file_len;
+	char *spd_file;
+
+	spd_gpio[0] = get_gpio(SPD_GPIO_BIT0);
+	spd_gpio[1] = get_gpio(SPD_GPIO_BIT1);
+	spd_gpio[2] = get_gpio(SPD_GPIO_BIT2);
+
+	spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0];
+
+	printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n",
+	       spd_index,
+	       spd_bits[2], spd_gpio[2],
+	       spd_bits[1], spd_gpio[1],
+	       spd_bits[0], spd_gpio[0]);
+
+	spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	if (spd_index > 3)
+		pei_data->dimm_channel1_disabled = 3;
+
+	if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+		spd_index = 0;
+	}
+
+	if (spd_file_len < SPD_LEN)
+		die("Missing SPD data.");
+
+	memcpy(pei_data->spd_data[0][0],
+		spd_file + spd_index, SPD_LEN);
+	/* Index 0-2 are 4GB config with both CH0 and CH1.
+	 * Index 4-6 are 2GB config with CH0 only. */
+	if (spd_index > 3)
+		pei_data->dimm_channel1_disabled = 3;
+	else
+		memcpy(pei_data->spd_data[1][0],
+			spd_file + spd_index, SPD_LEN);
+
+	/* Make sure a valid SPD was found */
+	if (pei_data->spd_data[0][0][0] == 0)
+		die("Invalid SPD data.");
+
+	mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/google/auron/spd/spd.h b/src/mainboard/google/auron/spd/spd.h
new file mode 100644
index 0000000000..27b1a4e226
--- /dev/null
+++ b/src/mainboard/google/auron/spd/spd.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN			256
+
+#define SPD_DRAM_TYPE		2
+#define  SPD_DRAM_DDR3		0x0b
+#define  SPD_DRAM_LPDDR3	0xf1
+#define SPD_DENSITY_BANKS	4
+#define SPD_ADDRESSING		5
+#define SPD_ORGANIZATION	7
+#define SPD_BUS_DEV_WIDTH	8
+#define SPD_PART_OFF		128
+#define  SPD_PART_LEN		18
+
+/* Auron board memory configuration GPIOs */
+#define SPD_GPIO_BIT0		13
+#define SPD_GPIO_BIT1		9
+#define SPD_GPIO_BIT2		47
+
+struct pei_data;
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
+#endif