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authorSimon Yang <simon1.yang@intel.com>2022-04-22 14:07:16 +0800
committerFelix Held <felix-coreboot@felixheld.de>2022-04-27 17:15:13 +0000
commitdec327b03b2fbf6dc6f89599107f645ed6a5396f (patch)
tree5ab8728acb148be9d573416575c3f91f38a8b1c7 /src/mainboard/google/auron/cmos.layout
parent19788cd9a48b7ab302c50a2fd6818a172615d1e5 (diff)
soc/intel/jasperlake: Revert CdClock setting
Revert CdClock setting and use default value 0xff. Previous problem was fixed by Jasperlake FSP in version 1.3.09.31, so we can use the original CdClock setting in baseboard. BUG=b:206557434 BRANCH=dedede TEST="Built and verified on magolor platform to confirm FSP solution works" Cq-Depend: chrome-internal:4662167 Change-Id: I50d65e0caaf8f3f074322cff5bbdc68bdb1bbf78 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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