diff options
| author | Hung-Te Lin <hungte@chromium.org> | 2022-09-06 14:32:05 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-09-07 09:20:25 +0000 |
| commit | a01f8bc450d782c9b0859c8caaaa3df87fe5a854 (patch) | |
| tree | b6f301ea3e7d09e256489c7c3f5918211ff9473c /src/mainboard/google/asurada/mainboard.c | |
| parent | 70f30afa89b725aa8655bed881f823408ac54453 (diff) | |
soc/mediatek: a common implementation to register BL31 reset
The implementations of register_reset_to_bl31() are the same for
MedaiTek platforms, so we extract them to soc/common/bl31.c.
BUG=None
TEST=build pass
Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/mainboard/google/asurada/mainboard.c')
| -rw-r--r-- | src/mainboard/google/asurada/mainboard.c | 18 |
1 files changed, 3 insertions, 15 deletions
diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c index bbca4b83ba..ddc2be4e53 100644 --- a/src/mainboard/google/asurada/mainboard.c +++ b/src/mainboard/google/asurada/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <bl31.h> #include <bootmode.h> #include <console/console.h> #include <delay.h> @@ -10,6 +9,7 @@ #include <edid.h> #include <framebuffer_info.h> #include <gpio.h> +#include <soc/bl31.h> #include <soc/ddp.h> #include <soc/dpm.h> #include <soc/dsi.h> @@ -24,8 +24,6 @@ #include "gpio.h" -#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h> - #define MSDC0_BASE 0x11f60000 #define MSDC0_TOP_BASE 0x11f50000 @@ -53,17 +51,6 @@ #define GPIO_AP_EDP_BKLTEN GPIO(KPROW1) /* 152 */ #define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) /* 40 */ -static void register_reset_to_bl31(void) -{ - static struct bl_aux_param_gpio param_reset = { - .h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO }, - .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, - }; - - param_reset.gpio.index = GPIO_RESET.id; - register_bl31_aux_param(¶m_reset.h); -} - /* Override hs_da_trail for ANX7625 */ void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing) { @@ -161,7 +148,8 @@ static void mainboard_init(struct device *dev) configure_audio(); setup_usb_host(); - register_reset_to_bl31(); + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) + register_reset_to_bl31(GPIO_RESET.id, true); if (dpm_init()) printk(BIOS_ERR, "dpm init fail, system can't do DVFS switch\n"); |