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authorAngel Pons <th3fanbus@gmail.com>2019-04-18 15:46:35 +0200
committerNico Huber <nico.h@gmx.de>2019-06-17 08:16:46 +0000
commit9065657957f5cb8c5a02695af7528263cfdceeaa (patch)
tree3be74028142dd13fd8ada3790d442c039cb2f0b2 /src/mainboard/gigabyte
parent01c83a2e9975f71d53772a535cf13d3e76a46827 (diff)
src/mb/gigabyte/ga-h61m-s2pv: Correct devicetree
Subsystem IDs were missing and GPIO settings were wrong. Plus, the PCI bridge was erroneously enabled, this board uses an ITE IT8892E PCIe to PCI bridge instead. Tested, board still boots. Change-Id: Ieb9dd8c835bc3652e7a3a118feca5551196bb81b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb17
1 files changed, 10 insertions, 7 deletions
diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
index e382cbde7f..e4ec810d45 100644
--- a/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
@@ -30,6 +30,7 @@ chip northbridge/intel/sandybridge
end
register "pci_mmio_size" = "2048"
device domain 0x0 on
+ subsystemid 0x1458 0x5000 inherit
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16)
device pci 02.0 on end # Internal graphics VGA controller
@@ -57,7 +58,7 @@ chip northbridge/intel/sandybridge
device pci 1c.6 off end # Unused PCIe Port
device pci 1c.7 off end # Unused PCIe Port
device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 on end # PCI bridge
+ device pci 1e.0 off end # PCI bridge
device pci 1f.0 on # LPC bridge
chip superio/ite/it8728f
device pnp 2e.0 off end # Floppy, not routed.
@@ -84,13 +85,15 @@ chip northbridge/intel/sandybridge
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
- device pnp 2e.7 off # GPIO
- io 0x25 = 0x40
- io 0x27 = 0x10
- io 0x2c = 0x80
+ device pnp 2e.7 on # GPIO
+ irq 0x25 = 0x40
+ irq 0x27 = 0x10
+ irq 0x2c = 0x80
+ io 0x60 = 0x0000
io 0x62 = 0x0a00
- io 0xcb = 0x00
- io 0xf1 = 0x40
+ io 0x64 = 0x0000
+ irq 0xcb = 0x00
+ irq 0xf1 = 0x40
end
device pnp 2e.a off end # CIR, not routed.
end