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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-10 07:33:36 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2013-12-26 23:22:17 +0100
commit142b52cd322ff69afe974f90a446f62b193d120c (patch)
treebada24c0b138e115ebb705409dd7173f1640ac30 /src/mainboard/gigabyte
parent88a67f0cc9d0bec08a6cfa5b1c3f4198fd98ab4f (diff)
AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4524 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/gigabyte')
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c1
-rw-r--r--src/mainboard/gigabyte/m57sli/romstage.c1
-rw-r--r--src/mainboard/gigabyte/ma785gm/romstage.c1
-rw-r--r--src/mainboard/gigabyte/ma785gmt/romstage.c1
-rw-r--r--src/mainboard/gigabyte/ma78gm/romstage.c1
5 files changed, 0 insertions, 5 deletions
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 7be37db5bf..f770577ddf 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/sis/sis966/early_setup_ss.h"
-#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index 3073358479..88f3d2558a 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -74,7 +74,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "lib/generic_sdram.c"
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index d4af41c1f5..ecee35b530 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -57,7 +57,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode.h"
#include "cpu/amd/model_10xxx/init_cpus.c"
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index d4af41c1f5..ecee35b530 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -57,7 +57,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode.h"
#include "cpu/amd/model_10xxx/init_cpus.c"
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 0840b1f62a..bd9011e74d 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -61,7 +61,6 @@ static int spd_read_byte(u32 device, u32 address)
#include "northbridge/amd/amdfam10/pci.c"
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode.h"
#include "cpu/amd/model_10xxx/init_cpus.c"