diff options
| author | John Zhao <john.zhao@intel.com> | 2022-01-13 09:09:05 -0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-16 13:20:06 +0000 |
| commit | 0f76a18c3a70fbdb1505a7e23b554026596be5c2 (patch) | |
| tree | 444f801f65c5f1ee9903d4c4a35e1a9974529043 /src/mainboard/gigabyte | |
| parent | ac24a96579d1b26978081b7cf29874474aabc525 (diff) | |
soc/intel/denverton_ns: Add the Primary to Sideband Bridge definition
This change adds the Primary to Sideband Bridge(B0, D31, F1)
definition for the platform in order to maintain the common block
API build.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1c4ddfce6cc6e41b2c63f99990d105b4bbb6f175
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/mainboard/gigabyte')
0 files changed, 0 insertions, 0 deletions