diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
| commit | d773fd370a92a6da2f7dbf91c085eb0df1f6f30d (patch) | |
| tree | fdaa9bd6278f4772c318d105e92a7cfdbc884521 /src/mainboard/gigabyte/ma78gm/romstage.c | |
| parent | 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a (diff) | |
Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
- spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
romstage.c files and lots of spd_addr.h files. Don't even bother for
those spd_addr.h which aren't even actually used, drop them right away.
- Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
and 0xa0 with (DIMM0 << 1) where appropriate.
- Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
- VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
- VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
- alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
- Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/gigabyte/ma78gm/romstage.c')
| -rw-r--r-- | src/mainboard/gigabyte/ma78gm/romstage.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a61be0a9ab..dcd523f057 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -86,10 +86,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { |