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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-10-13 15:01:15 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-10-28 16:56:55 +0200
commite1c36aecd8c5ad580595da58e180b06195df5f00 (patch)
tree142f543da79ab2090b895e0e1913e0d7aec821c8 /src/mainboard/gigabyte/ma785gmt/acpi/sata.asl
parent78f73353a3c0b7e3e59d0372f02dc1c37b226ac4 (diff)
pcengines/apu1: Add RS485 configuration
In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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