mb/gigabyte/ga-h61m-series: Initial GA-H61M-S2P-R3 bringup

Working:
 - Both DIMM slots
 - All Rear USB 2.0 ports
 - Integrated graphics (libgfxinit)
 - Realtek RTL8111F GbE
 - Flashing internally with flashrom (Note: Works from stock too
        due to Gigabyte not following Intel recommendations,
        confusing ME)
 - SeaBIOS (1.16.3) to boot Arch Linux Installer
 - EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer
 - Audio output (green jack, rear)
 - S3 suspend/resume
 - VBT

Untested for now (i.e. should work, will eventually test):
 - EHCI debug
 - Front USB 2.0 ports
 - The other audio jacks
 - PCIe ports
 - Non-Linux OSes

Untestable (i.e. cannot test due to unavailable hardware):
 - PS/2 port
 - Serial port
 - SATA ports

Not working:
 - USB 3.0 ports: The on-board VLI VL805 does not have a flash chip,
   so its firmware needs to be loaded on each boot. However,
   documentation about the (chip-specific) firmware loading procedure
   is nowhere to be found.
 - Super I/O automatic fan control: not yet implemented in coreboot.
   To control fans, use software fan control methods in the meantime.

Change-Id: I106c195c890823f07227739c6b30133b996f6510
Signed-off-by: PugzAreCute <me@pugzarecute.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

4 files changed, 296 insertions, 0 deletions

diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/data.vbt b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/data.vbt
new file mode 100644
index 0000000000..bd50743344
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/data.vbt
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/gpio.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/gpio.c
new file mode 100644
index 0000000000..d6a62515fb
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_HIGH,
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio35 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c
new file mode 100644
index 0000000000..3856bb0ca1
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/hda_verb.c
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0887,	/* Realtek ALC887 */
+	0x1458a002,	/* Subsystem ID */
+	15,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(2, 0x1458a002),
+	AZALIA_PIN_CFG(2, 0x11, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, 0x12, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, 0x14, 0x01014410),
+	AZALIA_PIN_CFG(2, 0x15, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, 0x16, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, 0x17, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
+	AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
+	AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
+	AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(2, 0x1c, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
+	AZALIA_PIN_CFG(2, 0x1e, AZALIA_PIN_CFG_NC(0)),
+	AZALIA_PIN_CFG(2, 0x1f, AZALIA_PIN_CFG_NC(0)),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/overridetree.cb
new file mode 100644
index 0000000000..fbebf1c830
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-s2p-r3/overridetree.cb
@@ -0,0 +1,78 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1458 0x5001 inherit
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{1, 6, 0},
+				{1, 6, 0},
+				{1, 6, 1},
+				{1, 6, 1},
+				{1, 6, 2},
+				{1, 6, 2},
+				{1, 6, 3},
+				{1, 6, 3},
+				{1, 6, 4},
+				{1, 6, 4},
+				{1, 6, 6},
+				{1, 6, 5},
+				{1, 6, 5},
+				{1, 6, 6},
+			}"
+
+			device ref pcie_rp1 on  end	# PCIe x1 Port (PCIEX1)
+			device ref pcie_rp2 on  end	# VIA Labs VL805 USB 3.0
+			device ref pcie_rp3 off end
+			device ref pcie_rp4 off end
+			device ref pcie_rp5 on		# Realtek RTL8111F GbE NIC
+				device pci 00.0 on
+					subsystemid 0x1458 0x8892
+				end
+			end
+			device ref pcie_rp6 on  end	# ITE IT8892F PCIe to PCI bridge
+
+			device ref lpc on
+				chip superio/ite/it8728f
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 on		# COM1
+						io  0x60 = 0x03f8
+						irq 0x70 = 0x04
+					end
+					device pnp 2e.2 off end		# COM2
+					device pnp 2e.3 on		# Parallel port
+						io  0x60 = 0x0378
+						irq 0x70 = 0x05
+						drq 0x74 = 0x04
+					end
+					device pnp 2e.4 on		# Environment Controller
+						io  0x60 = 0x0a30
+						irq 0x70 = 0x09
+						io  0x62 = 0x0230
+					end
+					device pnp 2e.5 on		# Keyboard
+						io  0x60 = 0x0060
+						irq 0x70 = 0x01
+						io  0x62 = 0x0064
+					end
+					device pnp 2e.6 on		# Mouse
+						irq 0x70 = 0x0c
+					end
+					device pnp 2e.7 on		# GPIO
+						irq 0x25 = 0x40
+						irq 0x27 = 0x10
+						irq 0x2c = 0x80
+						io  0x60 = 0x0000
+						io  0x62 = 0x0a00
+						io  0x64 = 0x0000
+						irq 0x70 = 0x00
+						irq 0xcb = 0x00
+						irq 0xf1 = 0x42
+					end
+					device pnp 2e.a off end		# CIR
+				end
+			end
+		end
+	end
+end